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18-bit switchable active scsi bus terminator (110 w ) the mccs142235 ? is a precision 18bit switchable active scsi bus terminator. it is used in conjunction with a 2.85v regulator (mc34268). also provided is a localv cc (lv cc ) low voltage sense circuit to latch the enable state when a peripheral is shut down or loses power. when the device is enabled according to the truth table below, the mccs142235 provides 110 w precision resistor pullups to a 2.85v reference for termination of 18bits in a scsi standard bus system interface. when the switch is disabled, the device is in a high impedance state on all 18 bits. the low voltage sense circuit gives the device the ability to latch the current output state when power is removed from the lv cc pin. as long as termpwr remains, there is no interruption to the scsi bus when powering down a scsi peripheral, because the proper termination condition remains. in 8bit scsi applications (aao cable), only one `2235 is needed at each end of the scsi cable in order to terminate the 18 active signal lines. in 16bit wide scsi applications (apo cable), one `2235 and one `2234 (or two `2235s) would be needed at each end of the scsi cable in order to terminate the 27 active signal lines. for information on apower dissipation for active scsi terminators,o refer to on semiconductor application note an1408/d, available through the on semiconductor fax system, or through the on semiconductor literature distribution center. ? complies with scsi and scsi2 standards ? 18 switchable 110 w terminating resistors ? operating temperature range: 0 c to 70 c ? operating voltage range: 2.75 to 2.95v ? resistor tolerance 5.0% (over temperature and supply voltage ranges) ? localv cc (lv cc ) low voltage sense circuit truth table test enable output active 0 0 z mode 0 1 terminated test mode 1 x test mode 23 24 22 21 20 19 18 vreg 17 lv cc o18 o17 o16 o15 o14 o13 figure 1. 24lead pinout (top view) 2 1 34567 8 v ref enable o1 o2 o3 o4 o5 o6 16 9 o12 o7 15 10 o11 o8 14 11 o10 o9 13 12 test gnd mccs142235 on semiconductor ? semiconductor components industries, llc, 2001 august, 2001 rev. 3 1 publication order number: mccs142235/d mccs142235 18bit active scsi terminator (110 w ) dw suffix 24lead wide soic package case 751e04 fa suffix 32lead plastic fqfp package case 873a02
mccs142235 http://onsemi.com 2 heat sink* 1 2 o2 3 o3 4 o4 5 o5 6 o6 7 o7 8 heat sink* figure 2. 32lead pinout (top view) 24 heat sink* 23 o17 22 o16 21 o15 20 o14 19 o13 18 o12 17 heat sink* 9 10111213141516 32 31 30 29 28 27 26 25 heat sink* o1 enable vref vreg lv o18 heat sink* heat sink* o8 o9 gnd test o10 o11 heat sink* mccs142235 *note: all heat sink pins are electrically isolated from the circuit. tie to largest heat sink. cc 60k w 60k w test 20k w v ref lv cc 110 w output 18 enable logic & latch circuitry enable vreg + ring oscillator & charge pump 110 w 110 w output 2 output 1 circuit design patent pending 100k w figure 3. mccs142235 block diagram
mccs142235 http://onsemi.com 3 10 m f mc34268* v out v in 10 m f 2.85v system logic vreg lv cc vref enable mccs142235 o18 o1 5.0v 0.5v scsi receivers open collector scsi bus driver 5.0v 0.5v 1n5819 10 m f mc34268* v out v in 10 m f 2.85v system logic vreg lv cc vref enable mccs142235 o18 o1 5.0v 0.5v scsi receivers open collector scsi bus driver termpwr scsi bus 1 scsi bus 18 *for more application information refer to the mc34268 datasheet. device #1 device #2 figure 4. typical scsi bus configuration using the mccs142235 maximum ratings* symbol parameter value units vreg dc regulated power voltage (referenced to gnd) 0.5 to 3.0 v v in dc input voltage (referenced to gnd) for test/v ref pins 0.5 to vreg + 0.5 v v in dc input voltage (referenced to gnd) for lv cc /enable pins 0.5 to + 6.0 v v out dc output voltage (referenced to gnd) 0.5 to vreg +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, vreg and gnd pins 500 ma t stg storage temperature 65 to + 150 c t l lead temperature, 1mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e recommended operating conditions.
mccs142235 http://onsemi.com 4 recommended operating conditions symbol parameter min max units vreg dc regulated power voltage (referenced to gnd) 2.75 2.95 v v in , v out dc input voltage (test/v ref inputs) 0 vreg v v in dc input voltage (enable, lv cc inputs) 0 5.5 v t a operating temperature 0 70 c t r , t f input rise and fall time (all inputs but lv cc) 0 500 ns t r , t f input rise and fall time (lv cc) 0 no limit ns dc characteristics vreg 25 c 0 c to + 70 c symbol parameters (v) min max min max unit condition v ih min highlevel input voltage 2.85 2.0 2.0 v per truth table v il max lowlevel input voltage 2.85 0.8 0.8 v per truth table i in max input leakage current (enable input) 2.85 0.10 1.0 m a v in = gnd max input leakage current (test input) 2.85 0.10 1.0 m a v in = gnd max input leakage current (lv cc input) 2.85 0.10 1.0 m a v in = gnd v ref = gnd 2.85 100 200 m a v in = 5.5v v ref = gnd max input leakage current (v ref input) 2.85 0.10 1.0 m a v in = vreg lv cc = vreg i oz max output leakage current 2.85 0.50 5.0 m a per truth table v out = gnd or vreg i cc max quiescent supply current 2.85 1.0 10 m a v ref /lv cc = vreg enable/test = gnd max quiescent supply current (comparator active) 2.85 100 200 m a enable/v ref /test = gnd lv cc = 5.0v max quiescent supply current (comparator active/ termination active) 2.85 800 1000 m a test/v ref = gnd enable/lv cc = 5.0v i out = 0 m a termination resistor characteristics vreg (v) 35 c 0 c to + 70 c symbol parameters min max min max min max unit condition r110 output termination impedance (note 1.) 2.75 2.95 108.9 (note 1.) 111.1 (note 1.) 104.5 115.5 w per truth table 1. see figure 5, termination resistance versus regulated supply voltage and temperature. 110 w resistor target is at 35 c. temperature coefficient of resistance t c = 0.135 w / c typical.
mccs142235 http://onsemi.com 5 figure 5. termination resistance r110 ( w ) versus regulated supply voltage vreg (v) and temperature ( c) (model adj rsq = 0.9995) 2.75 2.77 2.79 2.81 2.83 2.85 2.87 2.89 2.91 2.93 2.95 vreg (v) 0 7 14 21 28 35 42 49 56 63 70 temperature ( c) r110 ( w ) 115 114 113 112 111 110 109 108 107 106 105 104 dc characteristics symbol parameter vreg (v) typical @ +25 c unit condition v t latch voltage (lv cc input) 2.85 3.70 v per truth table c out output capacitance high impedance 2.85 8.0 pf per truth table, output = 0v 45 w 65 w vreg output high impedance 10pf terminated figure 6. output impedance model
mccs142235 http://onsemi.com 6 ac characteristics (vreg = 2.85, c l = 50 pf, t r = t f = 6 ns) symbol parameters 0 c to + 70 c unit condition t (enable) max propagation delay, high impedance to termination, enable to outputs 100 m s per truth table t (disable) max propagation delay, termination to high impedance, enable to outputs 1.0 m s per truth table timing requirements (vreg = 2.85, c l = 50 pf, t r = t f = 6 ns) symbol parameters 25 c 0 c to + 70 c unit condition t setup min setup time, lv cc to enable 200 500 ns (see figure 7) t hold min hold time, lv cc to enable 50 100 ns (see figure 7) figure 7. timing requirements 0.0 v 0.0 v v cc v v cc v t hold t setup lv cc enable 3.7v 3.7v 50% 50% enabled disabled * if lv cc enable is grounded then the lv cc feature is disabled. mccs142235 applications information proper use of the lv cc feature the on semiconductor active scsi terminator chip incorporates features not available in competitor designs. a primary feature, known as alocal v cc sensingo, facilitates future migration to reliable software control of the termination state (either terminated or high impedance). when the enable pin is driven by internal logic within the scsi peripheral, it is essential that the peripheral be powered up. otherwise the enable signal to the termination chip may be invalid causing system bus failure due to improper termination. imagine a scsi system with a disk drive at one end of the bus which is providing termination to the bus via the mccs142235 device. a asmarto drive will be providing an enable signal to the termination chip through internal logic circuitry to ensure termination is present. in the event this same disk drive is powered down by a user while the bus is active, what becomes of the termination located within that drive? does it remain terminated? does it change state causing the system to crash? or does it go into an undetermined state? the termination power supply is always present on an operating scsi bus through the dedicated termpwr line. but the alocal v cc o power supply within each peripheral may be powered down at any time while the scsi bus is in operation. it is this local supply which powers the peripheral's logic chips and provides the enable signal to the scsi terminator chip. therefore, it is essential to maintain the proper enable signal to the switchable terminator even during peripheral power down. to avoid rendering the system inoperable while powering down a terminating peripheral, on semiconductor has an exclusive alocal v cc sensingo circuit on the mccs142235 which latches the enable state of the termination permanently during peripheral power loss. a comparator within the mccs142235 can be connected to the local
mccs142235 http://onsemi.com 7 power supply via the lv cc input. the lv cc level is monitored against an internal reference, and the current enable state is latched should lv cc drop below a predetermined value ( 3.70v). this comparator threshold is set sufficiently high to ensure that a valid logic state still exists on the ttllevel enable pin prior to latching. upon return of the local power supply, the enable path automatically becomes transparent, and the termination state returns to system control! the local v cc sensing feature has been designed to draw as little dc current as possible. flexibility has been designed into the mccs142235 to allow the local v cc sensing feature to be disabled when not required. in this disabled state, the dc bias current is completely removed and the enable latch remains transparent at all times. figure 8 shows the recommended connection scheme to utilize the lv cc latch feature. figure 9 shows the recommended connection scheme for applications in which the lv cc feature is not required the lv cc and v ref pins are shorted to vreg and the enable path remains permanently transparent. 17 o13 8 o7 18 o14 7 o6 19 o15 6 o5 20 o16 5 o4 21 o17 4 o3 22 o18 3 o2 23 2 o1 24 vreg 1 vref connect to 2.85v regulated supply. enable signal driven by logic chip output. 16 o12 9 o8 15 o11 10 o9 14 o10 11 enable 13 test 12 gnd connect to v cc supplying board-level logic. do not connect to termpwr. when lv cc ? 3.7v, the t ermination state will be de termined by the enable signal (per truth table). when lv cc ? 3.7v, the enable signal will be latched. ter mination will remain in the proper state as long as vreg (ie termpwr) is present. figure 8. recommended connection scheme to utilize lv cc feature lv cc
mccs142235 http://onsemi.com 8 17 o13 8 o7 18 o14 7 o6 19 o15 6 o5 20 o16 5 o4 21 o17 4 o3 22 o18 3 o2 23 2 o1 24 vreg 1 vref connect to 2.85v regulated supply. enable signal driven by hardware switch or jumper. 16 o12 9 o8 15 o11 10 o9 14 o10 11 enable 13 test 12 gnd enable latch will be transparent as long as vreg (ie termpwr) is present. dc standby current for all analog circuitry associated with lv cc will be eliminated. figure 9. recommended connection scheme to disable lv cc feature lv cc enable input application result a. no connection to enable enable input will be pulled alowo internally. termination will be disabled causing all outputs to be high impedance. b. single pole switch to supply enable input will be pulled alowo internally when the switch is open. enable input will be held ahigho when the switch is closed. the supply source in this case could be termpwr, vreg or v cc . c. double pole switch between this is a more expensive way to accomplish application b. above. it is more supply and gnd economical to allow the internal pulldown to provide the alowo input level. the supply source in this case could be termpwr, vreg or v cc . d. hardwired alowo the mccs142235 will be permanently disabled causing all outputs to be high impedance. e. hardwired ahigho the mccs142235 will be permanently enabled providing 110 w nominal impedance to each bus line. f. external logic driven with lv cc input connected to the local power supply and v ref connected to gnd, the localv cc sensing and enable latching feature will be active. if this feature is not desired, tie lv cc and v ref to vreg (per figure 9), and the enable state will follow the truth table.
mccs142235 http://onsemi.com 9 package dimensions fa suffix fqfp package case 873a02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 t z u t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z t-u m 0.20 (0.008) z ac
mccs142235 http://onsemi.com 10 package dimensions dw suffix soic package case 751e04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mccs142235 http://onsemi.com 11 notes
mccs142235 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mccs142235/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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